As System-on-Chip (SoC) designs proliferate in diverse critical computing systems including emerging internet-of-things (IoT) applications, they need to include a wide variety of highly sensitive secure assets and protect them. These on-chip assets include cryptographic and Digital Right Management (DRM) keys, firmware, fuses, premium content, and even the designs of valuable hardware intellectual properties (IPs) composing the design. Consequently, a significant component of modern SoC design involves developing techniques to explore, analyze, and develop resiliency mechanisms against attacks or vulnerabilities to security assets. SoC security attacks arise from a large number of sources, including untrusted third-party IPs in the hardware itself, malicious or vulnerable firmware and software, attacks on communication of the system with other devices, hardware Trojan attacks in different components of SoC, and even side-channel vulnerabilities through power and performance profiles. Countermeasures for security attacks are equally varied and diverse, and include their own architecture, design, implementation, and validation components. Indeed, security activities encompass the entire SoC life cycle, from architecture definition to post-silicon validation and even on-field patches. There is a critical need to develop innovative security architectures that are resilient to diverse attacks; design-for-security (DfS) solutions that can provide effective protection against specific attacks; as well as pre- and post-silicon security validation techniques to address the security issues. Researchers in FICS are actively exploring cross-layer comprehensive solutions for secure and trusted SoC operation with collaboration with industry. Of particular emphasis are the following topics: (1) Developing infrastructure IP for SoC security; (2) Security rule check at IP and SoC level; and (3) Trusted SoC design with untrusted components.