ISTFA 2017 Outstanding Paper Award
University of Florida Department of Electrical & Computer Engineering FICS Research Institute researchers Assistant Professor Navid Asadizanjani, Assistant Professor Domenic Forte, IEEE Fellow Intel Chair E. Young Endowed Chair Professor in Cybersecurity Mark Tehranipoor and collaborators achieved renowned recognition at the International Symposium for Testing and Failure Analysis (ISTFA) by receiving the 2017 Outstanding Paper Award for their work “Steps Toward Automated Deprocessing of Integrated Circuits.” Reverse engineering (RE) of electronic systems is performed for many different reasons, including, but not limited to, failure analysis and fault isolation, obsolescence management, proof of IP rights infringement, security assessment, development of attacks, and counterfeiting. Regardless of the goal, it is imperative that the community understands the requirements, complexities, and limitations of RE.
Deprocessing of ICs historically is a very challenging and time consuming process which employs a variety of mechanical and chemical process tools in combination with one or more imaging modalities to reconstruct the IC architecture. In this paper, FICS researchers have developed a programmatic workflow based on the Tescan system’s open platform that allows common python scripting API architecture between different tools, which can take advantage of evolving technologies in 2D/3D imaging, distributed instrument control, image processing, as well as automated mechanical/chemical deprocessing technology. With the help of Tescan FICS Research Institute partner researchers were able to employ this procedure through the use of the FERA instrument.
For the first time, tomographic reconstruction of different ICs including smartcards, processors, etc. was performed based upon automated back-side ultra-thinning coupled to automated gas-assisted plasma FIB delayering. “Our new approach is capable of reducing the very costs of reverse engineering ICs tremendously and in particular reducing the total time to reverse engineer an IC from few months down to few days” advised Dr. Asadizanjani.