Reusable hardware Intellectual Property (IP) based System-on-Chip (SoC) design has emerged as a pervasive design practice in the industry to dramatically reduce overall design effort while meeting aggressive time-to-market constraints. Grow align-items-centering reliance on these pre-verified hardware IPs, often gathered from untrusted third-party vendors, severely affects the security and trustworthiness of SoC based computing platforms. An important emerging concern with the hardware IPs acquired from external sources is that they may come with deliberate malicious implants to incorporate undesired functionality, undocumented test/debug interface working as hidden backdoor, or other integrity issues. There is a critical need to verify integrity and trustworthiness of a wide variety of hardware IPs. Researchers in FICS are exploring a comprehensive framework for IP security and trust verification through integration of threat models, trust analysis, and trust validation using a combination of simulation-based techniques and formal methods.