Dr. Farahmandi Receives $500K DARPA Grant to Enhance Chip Security, Speed Time to Market
ECE Assistant Professor and member of the Florida Institute for Cybersecurity (FICS) Research Farimah Farahmandi has been awarded a $500K grant from the Defense Advanced Research Projects Agency (DARPA) for her project, “Security-Aware High-Level Synthesis (SHINE).” The project, which simultaneously introduces enhanced security strategies into the chip manufacturing process while significantly shortening the time to market, comes at a time when there are significant global shortages and slowdowns in chip manufacturing.
Global chip manufacturing exists in an environment the pressure to get new products into the market as quickly as possible is incredibly intense. Especially driven by Internet of Things (IoT) devices, fierce competition and frantic innovation mean that in order to survive, products must hit the market as quickly and securely as possible. The chips powering the devices often have a time-to-market of six months to a year, an eternity in today’s market. Unfortunately, the result is the well-documented problem that security considerations are often the first to be ditched—testing and verifying that the chips are in fact functioning securely with no potential confidentiality or integrity violations is indeed time consuming and complex.
Secure by Construction
Research led by Dr. Farahmandi takes the novel approach of building the enhanced security into the design phase, removing the need to perform post-manufacture security testing and verification. This yields a safer chip that is “Secure by Construction,” yet is able to get to market more quickly. SHINE achieves this dual improvement by injecting a series of complex security rules to the high-level synthesis (HLS) tool that is used in the design phase. These rules—key protection, information isolation, and access controls—make the HLS tool security-aware, whereas it previously was optimized only for power efficiency, are, and functionality. SHINE shows great promise in reducing slowdowns in the chip design while creating a pathway for more secure chips and products.