Dr. Asadi (FICS) and Dr. Need (MSE) Partner on $270k SRC Project

Reconfigurable Hardware for Secure IC Packaging using Nano-electromechanical Systems

Published: September 2nd, 2021

Category: News, Slider

Our proposal presents a first-ever methodology to enable hardware reconfiguration of interconnects and I/O inside the package even after the chip is fabricated. The prime feature of this novel technique is the trusted designer or IP owner will have the flexibility of reconfiguring and obfuscating the golden hardware design throughout the supply chain. Unlike the traditional obfuscation methods, here, the hardware connections will be reconfigured and changed when the chip is functional. In other words, there will be two states of the hardware configuration for the interconnects and I/O’s – ON-state and OFF-state design. In the OFF-state design, the configuration will be random, and this random design will be used for fabrication, testing, and distribution. If any adversaries in the supply chain get access to this OFF-state design or chip fabricated using this design will not be functional. To bring the device into the ON-state, a separate boot code will be provided by the IP designer upon verification and authentication. In the ON-state, the hardware of the I/O’s will be reconfigured to the golden design and this design will be retained until the chip is operational. After the usage, the chip will reset back to the OFF-state, and the connections will be random again. Therefore, adversaries will not be able to extract the actual design of the package, as to see the golden-designed configuration, the device needs to be functional and should have the boot code provided by the IP owners upon authentication.